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? semiconductor components industries, llc, 2002 may, 2002 rev. 3 1 publication order number: mc33178/d mc33178, mc33179 low power, low noise operational amplifiers the mc33178/9 series is a family of high quality monolithic amplifiers employing bipolar technology with innovative high performance concepts for quality audio and data signal processing applications. this device family incorporates the use of high frequency pnp input transistors to produce amplifiers exhibiting low input offset voltage, noise and distortion. in addition, the amplifier provides high output current drive capability while consuming only 420 a of drain current per amplifier. the npn output stage used, exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low openloop high frequency output impedance, symmetrical source and sink ac frequency performance. the mc33178/9 family offers both dual and quad amplifier versions, and is available in dip and soic packages. ? 600 output drive capability ? large output voltage swing ? low offset voltage: 0.15 mv (mean) ? low t.c. of input offset voltage: 2.0 v/ c ? low total harmonic distortion: 0.0024% (@ 1.0 khz w/600 load) ? high gain bandwidth: 5.0 mhz ? high slew rate: 2.0 v/ s ? dual supply operation: 2.0 v to 18 v ? esd clamps on the inputs increase ruggedness without affecting device performance figure 1. representative schematic diagram (each amplifier) v ee v cc i ref v in + v in - i ref c c c m v o pdip8 p suffix case 626 so8 d suffix case 751 marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week dual quad pdip14 p suffix case 646 so14 d suffix case 751a device package shipping ordering information mc33178d so8 98 units/rail mc33178p pdip8 mc33179d so14 50 units/rail 55 units/rail mc33179dr2 so14 2500 tape & reel mc33178dr2 so8 2500 tape & reel mc33179p pdip14 25 units/rail 1 8 mc33178p awl yyww alyw 33178 1 8 1 14 mc33179p awlyyww 1 14 mc33179d awlyww 1 8 1 8 1 14 14 1 http://onsemi.com
mc33178, mc33179 http://onsemi.com 2 pin connections case 626/751 dual case 646/751a quad (top view) v ee inputs 1 inputs 2 output 2 output 1 v cc - - + + 1 2 3 4 8 7 6 5 (top view) 1 2 3 4 5 6 78 9 10 11 12 13 14 4 23 1 inputs 1 output 1 v cc inputs 2 output 2 output 4 inputs 4 v ee inputs 3 output 3 ++ ++ maximum ratings rating symbol value unit supply voltage (v cc to v ee) v s +36 v input differential voltage range v idr note 1 v input voltage range v ir note 1 v output short circuit duration (note 2) t sc indefinite sec maximum junction temperature t j +150 c storage temperature range t stg 60 to +150 c maximum power dissipation p d note 2 mw operating temperature range t a 40 to +85 c 1. either or both input voltages should not exceed v cc or v ee . 2. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded. (see power dissipation performance characteristic, figure 2.)
mc33178, mc33179 http://onsemi.com 3 dc electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics figure symbol min typ max unit input offset voltage (r s = 50 , v cm = 0 v, v o = 0 v) (v cc = +2.5 v, v ee = 2.5 v to v cc = +15 v, v ee = 15 v) t a = +25 c t a = 40 to +85 c 3 |v io | 0.15 3.0 4.0 mv average temperature coefficient of input offset voltage (r s = 50 , v cm = 0 v, v o = 0 v) t a = 40 to +85 c 3 v io / t 2.0 v/ c input bias current (v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c 4, 5 i ib 100 500 600 na input offset current (v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c |i io | 5.0 50 60 na common mode input voltage range ( v io = 5.0 mv, v o = 0 v) 6 v icr 13 14 +14 +13 v large signal voltage gain (v o = 10 v to +10 v, r l = 600 ) t a = +25 c t a = 40 to +85 c 7, 8 a vol 50 25 200 kv/v output voltage swing (v id = 1.0 v) (v cc = +15 v, v ee = 15 v) r l = 300 r l = 300 r l = 600 r l = 600 r l = 2.0 k r l = 2.0 k (v cc = +2.5 v, v ee = 2.5 v) r l = 600 r l = 600 9, 10, 11 v o + v o v o + v o v o + v o v o + v o +12 +13 1.1 +12 12 +13.6 13 +14 13.8 1.6 1.6 12 13 1.1 v common mode rejection (v in = 13 v) 12 cmr 80 110 db power supply rejection v cc /v ee = +15 v/ 15 v, +5.0 v/ 15 v, +15 v/ 5.0 v 13 psr 80 110 db output short circuit current (v id = 1.0 v, output to ground) source (v cc = 2.5 v to 15 v) sink (v ee = 2.5 v to 15 v) 14, 15 i sc +50 50 +80 100 ma power supply current (v o = 0 v) (v cc = 2.5 v, v ee = 2.5 v to v cc = +15 v, v ee = 15 v) mc33178 (dual) t a = +25 c t a = 40 to +85 c mc33179 (quad) t a = +25 c t a = 40 to +85 c 16 i d 1.7 1.4 1.6 2.4 2.6 ma
mc33178, mc33179 http://onsemi.com 4 ac electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics figure symbol min typ max unit slew rate (v in = 10 v to +10 v, r l = 2.0 k , c l = 100 pf, a v = +1.0 v) 17, 32 sr 1.2 2.0 v/ s gain bandwidth product (f = 100 khz) 18 gbw 2.5 5.0 mhz ac voltage gain (r l = 600 , v o = 0 v, f = 20 khz) 19, 20 a vo 50 db unity gain bandwidth (openloop) (r l = 600 , c l = 0 pf) bw 3.0 mhz gain margin (r l = 600 , c l = 0 pf) 21, 23, 24 a m 15 db phase margin (r l = 600 , c l = 0 pf) 22, 23, 24 m 60 deg channel separation (f = 100 hz to 20 khz) 25 cs 120 db power bandwidth (v o = 20 v pp, r l = 600 , thd 1.0%) bw p 32 khz total harmonic distortion (r l = 600 ,, v o = 2.0 v pp , a v = +1.0 v) (f = 1.0 khz) (f = 10 khz) (f = 20 khz) 26 thd 0.0024 0.014 0.024 % open loop output impedance (v o = 0 v, f = 3.0 mhz, a v = 10 v) 27 |z o | 150 differential input resistance (v cm = 0 v) r in 200 k differential input capacitance (v cm = 0 v) c in 10 pf equivalent input noise voltage (r s = 100 ,) f = 10 hz f = 1.0 khz 28 e n 8.0 7.5 nv/ hz equivalent input noise current f = 10 hz f = 1.0 khz 29 i n 0.33 0.15 pa/ hz figure 2. maximum power dissipation versus temperature figure 3. input offset voltage versus temperature for 3 typical units p(max), maximum power dissipation (mw) d t a , ambient temperature ( c) -60 -40 -20 0 20 40 60 80 100 120 180 160 140 mc33178p/9p mc33179d mc33178d v, input offset voltage (mv) io t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 unit 1 unit 2 unit 3 v cc = +15 v v ee = -15 v r s = 10 v cm = 0 v 2400 2000 1600 1200 800 400 0 4.0 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 -4.0
mc33178, mc33179 http://onsemi.com 5 v o , output voltage (v ) pp figure 4. input bias current versus common mode voltage figure 5. input bias current versus temperature figure 6. input common mode voltage range versus temperature figure 7. open loop voltage gain versus temperature figure 8. voltage gain and phase versus frequency figure 9. output voltage swing versus supply voltage i, input bias current (na) ib v cm , common mode voltage (v) -15 -10 -5.0 0 5.0 10 15 v cc = +15 v v ee = -15 v t a = 25 c t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 v cc = +15 v v ee = -15 v v cm = 0 v , input common mode voltage range (v) icr t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 v cc = +5.0 v to +18 v v ee = -5.0 v to -18 v v io = 5.0 mv t a , ambient temperature ( c) vol , open loop voltage gain (kv/v) -55 -25 0 25 50 75 100 12 5 v cc = +15 v v ee = -15 v f = 10 hz v o = 10 v to +10 v r l = 600 f, frequency (hz) vol a , open loop voltage gain (db) , excess phase (degrees) 2 3 4 5 6 7 8 9 10 20 80 100 120 140 160 180 200 220 240 260 280 f 1a) phase (r l = 600 ) 2a) phase (r l = 600 c l = 300 pf) 1b) gain (r l = 600 ) 2b) gain (r l = 600 , c l = 300 pf) v cc = +15 v v ee = -15 v v o = 0 v t a = 25 c 2b 1a 2a 1b v cc , |v ee|, supply voltage (v) 0 5.0 10 15 20 t a = 25 c r l = 10 k r l = 600 i, input bias current (na) ib v a 160 140 120 100 80 60 40 20 0 120 110 100 90 80 70 60 v cc v cc -0.5 v v cc -1.0 v v cc -1.5 v v cc -2.0 v v ee +1.0 v v ee +0.5 v v ee 250 200 150 100 50 0 50 40 30 20 10 0 -10 -20 -30 -40 -50 40 35 30 25 20 15 10 5.0 0
mc33178, mc33179 http://onsemi.com 6 v o , output voltage (v ) pp source sink v cc = +15 v v ee = -15 v v id = 1.0 v r l < 10 t a = -55 to +125 c v cc = +15 v v ee = -15 v v cc = 1.5 v -psr +psr - + v o a dm psr = 20 log v cc v ee v o /a dm v cc figure 10. output saturation voltage versus load current figure 11. output voltage versus frequency figure 12. common mode rejection versus frequency over temperature figure 13. power supply rejection versus frequency over temperature figure 14. output short circuit current versus output voltage figure 15. output short circuit current versus temperature v sat i l , load current ( ma) 0 5.0 10 15 20 v cc = +5.0 v to +18 v v ee = -5.0 v to -18 v t a = +125 c t a = -55 c source sink t a = -55 c f, frequency (hz) 1.0 k 10 k 100 k 1.0 m v cc = +15 v v ee = -15 v r l = 600 a v = +1.0 v thd = 1.0% t a = 25 c f, frequency (hz) cmr, common mode rejection (db) 10 100 1.0 k 10 k 100 k 1.0 m v cc = +15 v v ee = -15 v v cm = 0 v v cm = 1.5 v t a = -55 to +125 c psr, power supply rejection (db) f, frequency (hz) 10 100 1.0 k 10 k 100 k 1.0 m i, output short circuit current (ma) sc -15 -9.0 -3.0 0 3.0 9.0 15 source sink v cc = +15 v v ee = -15 v v id = 1.0 v i, output short circuit current (ma) sc t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 , output saturation voltage (v) t a = +125 c v o , output voltage (v) v cc v cc -1.0 v v cc -2.0 v v ee +2.0 v v ee +1.0 v v ee 28 24 20 16 8.0 4.0 0 12 120 100 80 60 40 20 0 120 100 80 60 40 20 0 100 80 60 40 20 0 100 90 80 70 60 50 cmr = 20 log - + v cm v o x a dm a dm d v cm v o
mc33178, mc33179 http://onsemi.com 7 2b 1a 1b 2a 1a) phase v cc =18 v, v ee = -18 v 2a) phase v cc 1.5 v, v ee = -1.5 v 1b) gain v cc = 18 v, v ee = -18 v 2b) gain v cc = 1.5 v, v ee = -1.5 v t a = 25 c r l = c l = 0 pf t a = +125 c t a = +25 c t a = -55 c i , supply current/amplifier ( a) figure 16. supply current versus supply voltage with no load figure 17. normalized slew rate versus temperature figure 18. gain bandwidth product versus temperature figure 19. voltage gain and phase versus frequency figure 20. voltage gain and phase versus frequency figure 21. open loop gain margin versus temperature v cc, |v ee | , supply voltage (v) cc m 0 2.0 4.0 6.0 8.0 10 12 14 16 18 t a , ambient temperature ( c) sr, slew rate (normalized) -55 -25 0 25 50 75 100 125 v cc = +15 v v ee = -15 v v in = 20 v pp t a , ambient temperature ( c) gbw, gain bandwidth product (mhz) -55 -25 0 25 50 75 100 125 v cc = +15 v v ee = -15 v f = 100 khz r l = 600 c l = 0 pf f, frequency (hz) a , voltage gain (db) v , excess phase (degrees) 100 k f 1.0 m 10 m 100 m gain phase v cc = +15 v v ee = -15 v r l = 600 t a = 25 c c l = 0 pf f, frequency (hz) a, voltage gain (db) v , phase (degrees) 100 k f 1.0 m 10 m 100 m t a , ambient temperature ( c) a , open loop gain margin (db) m -55 -25 0 25 50 75 100 12 5 v cc = +15 v v ee = -15 v r l = 600 c l = 10 pf c l = 100 pf c l = 300 pf 625 500 375 250 125 0 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 10 8.0 6.0 4.0 2.0 0 50 40 30 20 10 0 -10 -20 -30 -40 -50 50 40 30 20 10 0 -10 -20 -30 -40 -50 15 12 9.0 6.0 3.0 0 v o 100 pf 600 - + v in 80 100 120 140 160 180 200 220 240 260 280 80 100 120 140 160 180 200 220 240 260 280
mc33178, mc33179 http://onsemi.com 8 v cc = +15 v v o = 2.0 v pp v ee = -15 v t a = 25 c r l = 600 a v = 1000 a v = 100 a v = 10 a v = 1.0 figure 22. phase margin versus temperature figure 23. phase margin and gain margin versus differential source resistance figure 24. open loop gain margin and phase margin versus output load capacitance figure 25. channel separation versus frequency figure 26. total harmonic distortion versus frequency figure 27. output impedance versus frequency f m v cc = +15 v v ee = -15 v r l = 600 c l = 10 pf c l = 100 pf c l = 300 pf t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 , phase margin (degrees) r t , differential source resistance ( ) a, gain margin (db) m 100 1.0 k 10 k 100 k m f , phase margin (degrees) gain margin phase margin v cc = +15 v v ee = -15 v r t = r 1 +r 2 v o = 0 v t a = 25 c a, open loop gain margin (db) m m c l , output load capacitance (pf) f 10 100 1.0 k , phase margin (degrees) phase margin gain margin v cc = +15 v v ee = -15 v v o = 0 v f, frequency (hz) cs, channel separation (db) 100 1.0 k 10 k 100 k 1.0 m drive channel v cc = +15 v c ee = -15 v r l = 600 t a = 25 c f, frequency (hz) thd, total harmonic distortion (%) 10 100 1.0 k 10 k 100 k f, frequency (hz) |z|, output impedance () o w 1.0 k 10 k 100 k 1.0 m 10 m 1. a v = 1.0 2. a v = 10 3. a v = 100 4. a v = 1000 v cc = +15 v v ee = -15 v v o = 0 v t a = 25 c 3 4 21 60 50 40 30 20 10 0 12 10 8.0 6.0 4.0 2.0 0 18 15 12 9.0 6.0 3.0 0 150 140 130 120 110 100 10 1.0 0.1 0.01 500 400 300 200 100 0 60 50 40 30 20 10 0 60 50 40 30 0 10 20 v in r 2 r 1 v o - + v o 600 - + v in c l
mc33178, mc33179 http://onsemi.com 9 figure 28. input referred noise voltage versus frequency figure 29. input referred noise current versus frequency figure 30. percent overshoot versus load capacitance figure 31. noninverting amplifier slew rate figure 32. small signal transient response figure 33. large signal transient response t, time (2.0 s/div) t, time (5.0 s/div) v cc = +15 v v ee = -15 v a v = +1.0 r l = 600 c l = 100 pf t a = 25 c t, time (2.0 ns/div) v o f, frequency (hz) 10 100 1.0 k 10 k 10 k e, input referred noise voltage () n nv/ hz v cc = +15 v v ee = -15 v t a = 25 c f, frequency (hz) i, input referred noise current () n 10 100 1.0 k 10 k 100 k v cc = +15 v v ee = -15 v t a = 25 c pa/ hz c l , load capacitance (pf) percent overshoot (%) 10 100 1.0 k 10 k v cc = +15 v v ee = -15 v t a = 25 c r l = 600 r l = 2.0 k v cc = +15 v v ee = -15 v a v = +1.0 r l = 600 c l = 100 pf t a = 25 c v cc = +15 v v ee = -15 v a v = +1.0 r l = 600 c l = 100 pf t a = 25 c , output voltage (50 mv/div) v o , output voltage (5.0 v/div) v o , output voltage (5.0 v/div) 20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 0.5 0.4 0.3 0.2 0.1 0 100 90 80 70 60 50 40 30 20 10 0 input noise voltage test circuit + v o - v o input noise current test circuit r s (r s = 10 k ) + -
mc33178, mc33179 http://onsemi.com 10 10 k a1 to receiver + - 1.0 f 300 200 k 120 k 2.0 k a2 820 1n4678 tip phone line ring a3 v r from microphone - - + + 10 k 10 k 10 k v r 10 k 0.05 f figure 34. telephone line interface circuit application information this unique device uses a boosted output stage to combine a high output current with a drain current lower than similar bipolar input op amps. its 60 phase margin and 15 db gain margin ensure stability with up to 1000 pf of load capacitance (see figure 24). the ability to drive a minimum 600 load makes it particularly suitable for telecom applications. note that in the sample circuit in figure 34 both a2 and a3 are driving equivalent loads of approximately 600 the low input offset voltage and moderately high slew rate and gain bandwidth product make it attractive for a variety of other applications. for example, although it is not single supply (the common mode input range does not include ground), it is specified at +5.0 v with a typical common mode rejection of 110 db. this makes it an excellent choice for use with digital circuits. the high common mode rejection, which is stable over temperature, coupled with a low noise figure and low distortion, is an ideal op amp for audio circuits. the output stage of the op amp is current limited and therefore has a certain amount of protection in the event of a short circuit. however, because of its high current output, it is especially important not to allow the device to exceed the maximum junction temperature, particularly with the mc33179 (quad op amp). shorting more than one amplifier could easily exceed the junction temperature to the extent of causing permanent damage. stability as usual with most high frequency amplifiers, proper lead dress, component placement, and pc board layout should be exercised for optimum frequency performance. for example, long unshielded input or output leads may result in unwanted input/output coupling. in order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. this not only minimizes the input pole frequency for optimum frequency response, but also minimizes extraneous apick upo at this node. supplying decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. additional stability problems can be caused by high load capacitances and/or a high source resistance. simple compensation schemes can be used to alleviate these effects.
mc33178, mc33179 http://onsemi.com 11 if a high source of resistance is used (r1 > 1.0 k ), a compensation capacitor equal to or greater than the input capacitance of the op amp (10 pf) placed across the feedback resistor (see figure 35) can be used to neutralize that pole and prevent outer loop oscillation. since the closed loop transient response will be a function of that capacitance, it is important to choose the optimum value for that capacitor. this can be determined by the following equation: (1) c c (1 [r1 r2]) 2 c l (z o r 2 ) where: z o is the output impedance of the op amp. for moderately high capacitive loads (500 pf < c l < 1500 pf) the addition of a compensation resistor on the order of 20 between the output and the feedback loop will help to decrease miller loop oscillation (see figure 36). for high capacitive loads (c l > 1500 pf), a combined compensation scheme should be used (see figure 37). both the compensation resistor and the compensation capacitor affect the transient response and can be calculated for optimum performance. the value of c c can be calculated using equation (1). the equation to calculate r c is as follows: (2) r c z o r1 r2 figure 35. compensation for high source impedance figure 36. compensation circuit for moderate capacitive loads figure 37. compensation circuit for high capacitive loads r2 - + r1 z l c c r2 r c c l r1 - + r2 c c r c c l r1 - +
mc33178, mc33179 http://onsemi.com 12 package dimensions pdip8 p suffix case 62605 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 so8 d suffix case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244
mc33178, mc33179 http://onsemi.com 13 package dimensions pdip14 p suffix case 64606 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n t 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 so14 d suffix case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc33178, mc33179 http://onsemi.com 14 notes
mc33178, mc33179 http://onsemi.com 15 notes
mc33178, mc33179 http://onsemi.com 16 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33178/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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